Shromona Ghosh picture

Shromona Ghosh


I am a PhD Candidate in the Electrical Engineering and Computer Science Department, University of California at Berkeley, advised by Prof. Sanjit Seshia and Prof. Alberto Sangiovanni-Vincentelli. I also work closely with Prof, Claire Tomlin. Previously, I have interned at Texas Instruments (Summer 2012), Cadence Design Systems (Summer 2014), Micrsoft AI Research Labs (Summer 2017) and Stanford Research Institute (Summer 2018).

My research interests lie in the intersection of Formal Methods (Verification and Synthesis), Control Theory and Machine Learning (ML). Particularly, my research focuses on:

Developing formal analysis techniques and tools for analyzing safety-critical systems with ML components such as Perception Systems, Reinforcement Learning Controllers, Data-Driven system models
Utilize the analysis techniques to build robust and safe controllers for safety-critical autonomous systems
Bridging the simulation to real-world gap to provide safety guarantees

Conference Publications

SOTER: Programming Safe Robotics System using Runtime Assurance
A. Desai, S. Ghosh, S. Seshia, N. Shankar, A. Tiwari
arXiv Preprint 2018.

Context-Specific Validation of Data-Driven Models
S. Bansal*, S. Ghosh*, A. Sangiovanni-Vincentelli, S.A. Seshia and C.J. Tomlin
arXiv Preprint 2018.

Scenic: A language for Scenario Specification and Scene Generation
D. Fremont, X. Yue, T. Dreossi, S. Ghosh, A. Sangiovanni-Vincentelli, S. A. Seshia
ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI) 2019 (In Subimssion)

Verifying Controllers Against Adversarial Examples with Bayesian Optimization
S. Ghosh, F. Berkenkamp, G. Ranade, S. Qadeer, A. Kapoor
International Conference on Robotics and Automation (ICRA), 2018

Formal Specification for Deep Neural Networks
S. Seshia, A. Desai, T. Dreossi, D. Fremont, S. Ghosh, E. Kim, S. Shivakumar, M. Vazquez-Chanlatte, X. Yue
International Symposium on Automated Technology for Verification and Analysis (ATVA), 2018 (invited paper)

Counterexample-Guided Data Augmentation
T. Dreossi, S. Ghosh, X. Yue, K. Kuetzer, A. Sangiovanni-Vincentelli, S. Seshia
International Joint Conference on Artificial Intelligence (IJCAI), 2018

Time Series Learning using Monotonic Logical Properties
M. Vazquez-Chanlatte, S. Ghosh, J. Deshmukh, A. Sangiovanni-Vincentelli, S. Seshia
International Conference on Runtime Verification (RV), 2018

Dominant Strategies for Continuous Two-Player Zero-Sum Games
M. Vazquez-Chanlatte, S. Ghosh, V. Raman, A. Sangiovanni-Vincentelli, S. Seshia
FAC Conference on Analysis and Design of Hybrid Systems (ADHS), 2018

Diagnosis and Repair for Synthesis from Signal Temporal Logic Specifications
S. Ghosh, D. Sadigh, P. Nuzzo, V. Raman, A. Donze, A. Sangiovanni Vincentelli, S. Sastry and S. Seshia
ACM International Conference on Hybrid Systems Computation and Control (HSCC), 2016 (passed Repeatibility Evaluation).

Robust Online Monitoring of Signal Temporal Logic
J. Deshmukh, A. Donze, S. Ghosh, X. Jin, G. Juniwal and S. Seshia
International Conference on Runtime Verification (RV), 2015
Best Paper Award

Journal Publications

A Minimum Discounted Reward Hamilton-Jacobi Formulation for Computing Reachable Sets
A. Akametalu, S. Ghosh, J. Fisac, C. Tomlin
IEEE Transactions on Automatic Control (TAC), 2019 (Under Review)
Robust Online Monitoring of Signal Temporal Logic
J. Deshmukh, A. Donze, S. Ghosh, X. Jin, G. Juniwal and S. Seshia
Formal Methods in System Design (FMSD), 2017

Workshop Publications

Testing of Convolutional Neural Networks for Autonomous Driving
T. Dreossi*, S. Ghosh*, A. Sangiovanni-Vincentelli, S. Seshia
Reliable Machine Learning in the Wild (RMLW) Workshop at International Conference on Machine Learnin (ICML), 2017

Industrial Publications

SmartScan + OPMISR : A Novel Scan Compression Architecture for Multi-Site Testing
R. Parekhji, R. Chandel, S. Ghosh, R. Suthapalli, G. Swathi and D.Gaur
Cadence (CDN) Live Conference 2012
Best Paper Award in Digital Front End Track